การบรรจุระดับเวเฟอร์แบบพัดลมออก (FOWLP) has emerged as a game-changer in semiconductor packaging.
It enables chips to be packaged with more I/O (input/output) density, superior electrical performance, and reduced size, meeting the needs of industries like 5G, automotive, AI, and consumer electronics.
What is Fan-Out Wafer Level Packaging?
Fan-Out Wafer Level Packaging (FOWLP) is an advanced semiconductor packaging technology in which a chip is embedded in a mold compound and rerouted to external contacts through a Redistribution Layer (RDL), without using a traditional substrate.
In simpler terms, imagine placing a small die (chip) on a flat surface and covering it with a protective shell. Then, metal traces are built outward, “fanned out” from the chip to make electrical connections. This process results in a package that behaves like a mini printed circuit board (PCB), only at a micron-scale level.
Unlike fan-in packaging, where interconnects remain within the die area, fan-out extends them outside, allowing higher I/O count, better signal integrity, and more layout freedom.
Why is Fan-Out Wafer Level Packaging Used?
FOWLP is used because it addresses the critical demands of modern microelectronics:
- Miniaturization: Enables ultra-thin and compact packages required in smartphones and wearable tech.
- Performance: Reduces parasitic inductance and capacitance due to shorter electrical paths.
- Thermal Efficiency: Spreads heat better than conventional packaging, increasing reliability.
- ประสิทธิภาพต้นทุน: Removes the need for an interposer or organic substrate used in BGA or flip-chip packages.
For example, Apple’s A-series chips, used in iPhones, leverage a form of FOWLP called Integrated Fan-Out (InFO) to pack high performance into thin enclosures.
FOWLP Applications
Fan-Out Wafer Level Packaging finds wide application use in sectors that demand high-density packaging and excellent thermal/electrical performance. This includes:
1. Mobile & Consumer Electronics
FOWLP allows compact, high-performance packaging for SoCs and RF modules by integrating components without substrates, reducing size while improving speed, power efficiency, and signal quality.
2. Automotive Electronics
FOWLP supports radar sensors and ADAS systems by offering thermal stability and high-density interconnects, critical for reliable, space-efficient automotive-grade electronic modules.
3. IoT Devices
Fan-Out packaging enables ultra-compact chips with efficient thermal handling and low-power interconnects, ideal for real estate-constrained IoT devices needing high connectivity in small packages.
4. Wearables & Medical Devices
FOWLP’s thin form factor and biocompatible mold materials make it suitable for implantable and wearable electronics, enhancing performance, comfort, and long-term reliability.
5. High-Performance Computing (HPC)
Multi-die integration via FOWLP supports chiplet-based HPC systems, allowing dense, high-speed interconnects and scalable processing power within a small, energy-efficient footprint. Its ability to support System-in-Package (SiP) designs makes it ideal for integrating memory, sensors, antennas, and logic onto one platform.
FOWLP Process Flow
The Fan-Out process begins after wafer fabrication and involves the following steps:
1. Wafer Dicing
Wafer dicing involves cutting a processed wafer into individual bare dies using precision blades or lasers. Accurate dicing prevents micro-cracks, ensuring die integrity and preparing each chip for further packaging steps without compromising reliability.
2. Die Placement on Carrier
Individual dies are mounted face-down on a temporary carrier using automated pick-and-place systems. Precise alignment ensures proper routing and connectivity in subsequent stages, directly impacting the accuracy of redistribution layers in fan-out packaging.
3. Mold Compound Application (Reconstitution)
A mold compound is dispensed over placed dies, embedding them in epoxy and creating a larger reconstituted wafer. This allows for fan-out area creation and sets the base for redistribution layer formation with extended routing space.
4. Wafer Thinning and Cleaning
The reconstituted wafer is ground to achieve uniform thickness and then cleaned using plasma or chemical processes. Thinning improves thermal performance and enables fine-pitch interconnects, while cleaning ensures adhesion and material compatibility in the RDL stage.
5. Redistribution Layer (RDL) Formation
Using photolithography and electroplating, fine copper lines are built to reroute connections from die pads outward. This fan-out architecture enables higher I/O count and improved electrical performance in compact semiconductor packages.
6. Bumping or Ball Drop
Solder balls are deposited on the RDL to form external interconnects. This enables electrical and mechanical connections to the final PCB. Controlled bumping ensures reliable mounting and signal integrity in high-speed applications.
7. Package Singulation
The completed reconstituted wafer is cut into individual packages using mechanical or laser dicing. Singulation finalizes the fan-out chip package, making it ready for testing and integration in system-level assemblies with high performance demands.
This entire process requires extreme accuracy. For example, die shift during mold curing can lead to misalignment in the RDL stage, which is one of the biggest challenges in high-density layouts.
What are the Advantages of FOWLP?
Higher I/O Density
FOWLP enables interconnects beyond the die edge using Redistribution Layers, allowing higher I/O count and compact routing, ideal for complex, high-performance semiconductor applications.
Lower Profile
By eliminating bulky substrates, FOWLP creates ultra-thin packages. This supports sleek product designs, especially in smartphones, wearables, and space-constrained electronics.
Improved Electrical & Thermal Performance
Shorter signal paths in FOWLP reduce parasitic effects and enhance heat dissipation, improving both speed and thermal reliability in dense chip configurations.
No Substrate Required
FOWLP removes the need for traditional substrates, cutting material costs and simplifying the package structure, leading to a more efficient and flexible supply chain.
Scalability
FOWLP supports integration of single or multiple dies, enabling modular system-in-package (SiP) and chiplet architectures for evolving high-density electronic requirements.
Types of Fan-Out Packaging
1. Standard Single-Die FOWLP
This packaging integrates a single die into a molded reconstituted wafer, extending connections outward via redistribution layers. It enables compact, low-cost packages ideal for RF chips and power management ICs with excellent thermal and electrical efficiency.
2. Multi-Die FOWLP
Multiple dies are embedded in a reconstituted wafer with carefully controlled spacing. Redistribution layers connect them within the same package, allowing compact multi-chip integration and reducing board-level complexity for devices like processors and sensors in one unit.
3. Fan-Out SiP (System-in-Package)
Combines a die with passive components, memory, and sensors within one molded structure. Redistribution layers interconnect all elements, creating a miniaturized system. This enhances performance and enables high-functionality modules in smartphones and RF front-end designs.
4. High-Density FOWLP / RDL Interposer
Serves as a high-density interconnect platform without requiring an organic interposer. It supports chiplet designs by enabling fine-line routing between multiple dies. Common in high-performance applications like AI accelerators, 5G SoCs, and advanced edge computing modules.
What are the Challenges in FOWLP Manufacturing?
Despite its benefits, FOWLP faces technical hurdles:
Die Shift During Mold Curing
Thermal expansion during molding can shift die positions, leading to RDL misalignment. Accurate placement ensures electrical connectivity and prevents yield loss in high-density layouts.
Warpage
Thermal stress between materials causes wafer warping post-molding. Controlled flatness is essential for reliable RDL formation, die bonding, and high-throughput assembly processes.
Material Stress
Stress between the mold, silicon, and RDL layers can lead to cracks or delamination. Managing this improves mechanical integrity and long-term package reliability.
Inspection Difficulty
Internal voids under the mold or RDL are hard to detect. Advanced imaging techniques like X-ray and CT ensure hidden defects are identified before final assembly.
Process Complexity
FOWLP involves more stages than traditional WLP, needing precise control and inline metrology. This complexity supports higher integration but demands rigorous process monitoring.
Role of Metrology & Inspection in FOWLP
Metrology in FOWLP verifies structural and dimensional accuracy at the micron level. It uses scientific, non-contact methods to detect defects early in the process. This ensures reliability, performance consistency, and supports high-yield semiconductor manufacturing.
การวัดด้วยแสง
Optical metrology captures 2D and 3D surface features using reflected light. It measures warpage, bump height, and surface variations with precision. This method ensures structural uniformity and supports tight design tolerances in FOWLP production.
X-ray and CT Imaging
X-ray and CT imaging detect hidden voids and structural defects inside solder joints and underfill layers. These non-destructive methods enhance reliability by identifying failures that are invisible on the surface during fan-out packaging.
Laser Profilometry
Laser profilometry uses focused beams to map bump height, coplanarity, and die shift. It provides high-resolution surface profiles, helping manufacturers maintain alignment and flatness critical for electrical contact in multi-layer packaging.
Ultrasonic Imaging
Ultrasonic imaging sends high-frequency sound waves into the package to assess internal bond integrity. It identifies weak or broken connections in wire bonds or die attach without damaging the package, ensuring long-term electrical performance.
Infrared Thermography
Infrared thermography visualizes heat distribution across a semiconductor package. It detects hidden defects like delamination or thermal stress zones, helping engineers prevent failures due to overheating or material separation in dense FOWLP designs.
VIEW Micro Metrology – Enabling Reliable Fan-Out Packaging
VIEW designs advanced optical metrology systems to support inspection needs inline, enabling high-throughput FOWLP production. With FOWLP requiring micron-level accuracy, VIEW Micro-Metrology delivers advanced inspection systems for RDL, bump, void, and bond integrity analysis. Our ระบบมาตรวิทยาเชิงแสง support semiconductor, medical, and electronics manufacturing lines with ultra-precise, high-speed measurements that integrate directly into process flow.
บทสรุป
Fan-Out Wafer Level Packaging is not just a trend; it’s a critical shift in semiconductor integration that supports the growing demand for performance, density, and form factor reduction. From smartphones to autonomous vehicles, FOWLP is shaping the next generation of electronics.
For accurate, inline inspection solutions built for FOWLP and high-density packaging, get in touch with VIEW ไมโครมาตรวิทยา, where precision meets performance.